View S-25A256B_4131324.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

S-25A256B www.sii-ic.com 125c operation spi serial e 2 prom for automotive ? seiko instruments inc., 2011 rev.1.0 _00 seiko instruments inc. 1 this ic is a spi serial e 2 prom which operates under the hi gh temperature, at high speed, with the wide range operation for automotive components. this ic has the capacity of 256 k-bit and the organization of 32768 words 8-bit. page write and sequential read are available. caution before using the product in automobile control uni t or medical equipment, contact to sii is indispensable. ? features ? operating voltage range read: 2.5 v ~ 5.5 v write: 2.5 v ~ 5.5 v ? operation frequency: 5.0 mhz max. ? write time: 5.0 ms max. ? spi mode (0, 0) and (1, 1) ? page write: 64 bytes / page ? sequential read ? write protect: software, hardware protect area: 25%, 50%, 100% ? monitoring of a write memory state by the st atus register ? function to prevent malfunction by monitoring clock pulse ? write protect function duri ng the low power supply voltage ? cmos schmitt input ( cs , sck, si, wp , hold ) ? endurance *1 : 10 6 cycle / word *2 (ta = + 25c) 3 10 5 cycle / word *2 (ta = + 125c) ? data retention: 100 years (ta = + 25c) 50 years (ta = + 125c) ? memory capacity: 256 k-bit ? initial shipment data: ffh, srwd = 0, bp1 = 0, bp0 = 0 ? burn-in specifications: wafer level burn-in ? lead-free (sn 100%), halogen-free *3 *1. refer to " ? endurance " for details. *2. for each address (word: 8-bit) *3. refer to " ? product name structure " for details. ? package ? 8-pin sop (jedec) 1 4 5 8 (5.0 6.0 t1.75 mm) remark refer to " 3. product name list " in " ? product name structure " for details of package and product. www.datasheet.co.kr datasheet pdf - http://www..net/
125c operation spi serial e 2 prom for automotive S-25A256B rev.1.0 _00 seiko instruments inc. 2 ? block diagram mode decoder status register address register data register wp cs hold si sck so vcc gnd memory cell array status memory cell array voltage detector read circuit clock counter y decoder x decoder input control circuit output control circuit step-up circuit page latch figure 1 www.datasheet.co.kr datasheet pdf - http://www..net/
125c operation spi serial e 2 prom for automotive rev.1.0 _00 S-25A256B seiko instruments inc. 3 ? product name structure 1. product name S-25A256B 0a ? j8t2 u 3 environmental code u: lead-free (sn 100%), halogen-free fixed product name S-25A256B: 256 k-bit fixed package name (abbreviation) and ic packing specification *1 j8t2: 8-pin sop ( jedec ) , ta p e *1. refer to the tape drawing. remark this ic is wafer level burn-in specification. 2. package table 1 package drawing codes package name dimension tape reel 8-pin sop (jedec) fj008-a-p-sd fj008-d-c-sd fj008-d-r-s1 3. product name list table 2 product name capacity package quantity S-25A256B0a-j8t2u3 256 k bit 8-pin sop (jedec) 4000 pcs / reel remark this ic is wafer level burn-in specification. ? pin configuration 1. 8-pin sop (jedec) table 3 pin no. symbol description 1 cs *1 chip select input 2 so serial data output 3 wp *1 write protect input 4 gnd ground 5 si *1 serial data input 6 sck *1 serial clock input 7 hold *1 hold input 8 vcc power supply 7 6 5 8 2 3 4 1 top view figure 2 *1. do not use it in "high-z". www.datasheet.co.kr datasheet pdf - http://www..net/
125c operation spi serial e 2 prom for automotive S-25A256B rev.1.0 _00 seiko instruments inc. 4 ? absolute maximum ratings table 4 item symbol absolute maximum rating unit power supply voltage v cc ? 0.3 to + 6.5 v input voltage v in ? 0.3 to + 6.5 v output voltage v out ? 0.3 to v cc + 0.3 v operation ambient temperature t opr ? 40 to + 125 c storage temperature t stg ? 65 to + 150 c caution the absolute maximum ra tings are rated values exceeding whic h the product could suffer physical damage. these values must therefore not be exceeded under any conditions. ? recommended operating conditions table 5 ta = ? 40c to + 125c item symbol condition min. max. unit read 2.5 5.5 v power supply voltage v cc write 2.5 5.5 v high level input voltage v ih v cc = 2.5 v to 5.5 v 0.7 v cc v cc + 1.0 v low level input voltage v il v cc = 2.5 v to 5.5 v ? 0.3 0.3 v cc v ? pin capacitance table 6 (ta = + 25c, f = 1.0 mhz, v cc = 5.0 v) item symbol condition min. max. unit input capacitance c in v in = 0 v ( cs , sck, si, wp , hold ) 8 pf output capacitance c out v out = 0 v (so) 10 pf ? endurance table 7 item symbol operation ambient temperature min. max. unit ta = + 25c 10 6 cycle / word *1 ta = ? 40c to + 85c 7 10 5 cycle / word *1 ta = ? 40c to + 105c 5 10 5 cycle / word *1 endurance n w ta = ? 40c to + 125c 3 10 5 cycle / word *1 *1. for each address (word: 8-bit) ? data retention table 8 item symbol operation ambient temperature min. max. unit ta = + 25c 100 year data retention ta = ? 40c to + 125c 50 year www.datasheet.co.kr datasheet pdf - http://www..net/
125c operation spi serial e 2 prom for automotive rev.1.0 _00 S-25A256B seiko instruments inc. 5 ? dc electrical characteristics table 9 ta = ? 40c to + 125c v cc = 2.5 v to 4.5 v f sck = 5.0 mhz v cc = 4.5 v to 5.5 v f sck = 5.0 mhz item symbol condition min. max. min. max. unit current consumption (read) i cc1 no load at so pin 2.0 2.5 ma table 10 ta = ? 40c to + 125c v cc = 2.5 v to 5.5 v f sck = 5.0 mhz item symbol condition min. max. unit current consumption (write) i cc2 no load at so pin 4.0 ma table 11 ta = ? 40c to + 125c v cc = 2.5 v to 4.5 v v cc = 4.5 v to 5.5 v item symbol condition min. max. min. max. unit standby current consumption i sb cs = v cc , so = open other inputs are v cc or gnd 8.0 10.0 a input leakage current i li v in = gnd to v cc 2.0 2.0 a output leakage current i lo v out = gnd to v cc 2.0 2.0 a v ol1 i ol = 2.0 ma 0.4 v low level output voltage v ol2 i ol = 1.5 ma 0.4 0.4 v v oh1 i oh = ? 2.0 ma 0.8 v cc v high level output voltage v oh2 i oh = ? 0.4 ma 0.8 v cc 0.8 v cc v www.datasheet.co.kr datasheet pdf - http://www..net/
125c operation spi serial e 2 prom for automotive S-25A256B rev.1.0 _00 seiko instruments inc. 6 ? ac electrical characteristics table 12 measurement conditions input pulse voltage 0.2 v cc to 0.8 v cc output reference voltage 0.5 v cc output load 100 pf table 13 ta = ? 40c to + 125c v cc = 2.5 v to 5.5 v item symbol min. max. unit sck clock frequency f sck 5.0 mhz cs setup time during cs falling t css.cl 90 ns cs setup time during cs rising t css.ch 90 ns cs deselect time t cds 90 ns cs hold time during cs falling t csh.cl 90 ns cs hold time during cs rising t csh.ch 90 ns sck clock time "h" *1 t high 90 ns sck clock time "l" *1 t low 90 ns rising time of sck clock *2 t rsk 1 s falling time of sck clock *2 t fsk 1 s si data input setup time t ds 20 ns si data input hold time t dh 30 ns sck "l" hold time during hold rising t skh.hh 70 ns sck "l" hold time during hold fa lling t skh.hl 40 ns sck "l" setup time during hold fa lling t sks.hl 0 ns sck "l" setup time during hold rising t sks.hh 0 ns disable time of so output *2 t oz 100 ns delay time of so output t od 70 ns hold time of so output t oh 0 ns rising time of so output *2 t ro 40 ns falling time of so output 2 t fo 40 ns disable time of so output during hold fa lling *2 t oz.hl 100 ns delay time of so output during hold rising *2 t od.hh 50 ns wp setup time t ws1 0 ns wp hold time t wh1 0 ns wp release / setup time t ws2 0 ns wp release / hold time t wh2 30 ns *1. the clock cycle of the sck clock (frequency f sck ) is 1 / f sck s. this clock cycle is determined by a combination of several ac characteristics. note that the clock cycle cannot be set as (1 / f sck ) = t low (min.) + t high (min.) by minimizing the sck clock cycle time. *2. these are values of sample and not 100% tested. table 14 ta = ? 40c to + 125c v cc = 2.5 v to 5.5 v item symbol min. max. unit write time t pr 5.0 ms www.datasheet.co.kr datasheet pdf - http://www..net/
125c operation spi serial e 2 prom for automotive rev.1.0 _00 S-25A256B seiko instruments inc. 7 so t csh.cl sck cs si t css.cl t ds t dh msb in lsb in t csh.ch t css.ch t cds t fsk t rsk high-z figure 3 serial input timing so sck hold cs si t skh.hl t oz.hl t od.hh t skh.hh t sks.hl t sks.hh figure 4 hold timing www.datasheet.co.kr datasheet pdf - http://www..net/
125c operation spi serial e 2 prom for automotive S-25A256B rev.1.0 _00 seiko instruments inc. 8 so sck cs si t high t oh t ro t oz t low t sck t od t fo t od t oh addr lsb in lsb out figure 5 serial output timing wp cs t wh1 t ws1 figure 6 valid timing in write protect wp cs t wh2 t ws2 figure 7 invalid timing in write protect www.datasheet.co.kr datasheet pdf - http://www..net/
125c operation spi serial e 2 prom for automotive rev.1.0 _00 S-25A256B seiko instruments inc. 9 ? pin functions 1. cs (chip select input) pin this is an input pin to set a chip in the select status. in t he "h" input level, this ic is in the non-select status and its output is "high-z". this ic is in standby as long as it is not in write inside. th is ic goes in active by setting the chip select to "l". input any instruction code after power-on and a falling of chip select. 2. si (serial data input) pin this pin is to input serial data. this pin receives an instruction code, an address and write data. this pin latches data at rising edge of serial clock. 3. so (serial data output) pin this pin is to output serial data. the data output changes at falling edge of serial clock. 4. sck (serial clock input) pin this is a clock input pin to set the timing of serial data. an instruction code, an addre ss and write data are received at a rising edge of clock. data is output during falling edge of clock. 5. wp (write protect input) pin write protect is purposed to pr otect the area size against the write instruction (bp1, bp0 in the status register). fix this pin "h" or "l" not to se t it in the floating state. refer to " ? protect operation " for details. 6. hold (hold input) pin this pin is used to pause serial communications wi thout setting this ic in the non-select status. in the hold status, the serial output goes in "high-z", the serial input and t he serial clock go in "don't care". during the hold operation, be sure to set this ic in active by setting the chip select ( cs pin) to "l". refer to " ? hold operation " for details. ? initial shipment data initial shipment data of all addresses is "ffh". moreover, initial shipment data of the status register nonvol atile memory is as follows. ? srwd = 0 ? bp1 = 0 ? bp0 = 0 www.datasheet.co.kr datasheet pdf - http://www..net/
125c operation spi serial e 2 prom for automotive S-25A256B rev.1.0 _00 seiko instruments inc. 10 ? instruction set table 15 is the list of instruction for this ic. the instruction is able to be input by changing the cs pin "h" to "l". input the instruction in the msb first. each in struction code is organized with 1-byte as shown below. if this ic receives any invalid instruction code, this ic goes in the non-select status. table 15 instruction set instruction code address data instruction operation sck input clock 1 to 8 sck input clock 9 to 16 sck input clock 17 to 24 sck input clock 25 to 32 wren write enable 0000 0110 wrdi write disable 0000 0100 rdsr read the status register 0000 0101 b7 to b0 output *1 wrsr write in the status register 0000 0001 b7 to b0 input read read memory data 0000 0011 a15 to a8 *2 a7 to a0 d7 to d0 output *3 write write memory data 0000 0010 a15 to a8 *2 a7 to a0 d7 to d0 input *1. sequential data reading is possible. *2. the higher addresses a15 = don't care. *3. after outputting data in the specified addr ess, data in the following address is output. ? operation 1. status register the status register's organization is below. the status register can write and read by a specific instruction. srwd 0 b7 b6 0 b5 0 b4 bp1 b3 bp0 b2 wel b1 wip b0 status register write disable block protect write enable latch write in progress figure 8 organization of status register the status / control bits of t he status register as follows. 1. 1 srwd (b7) : status register write disable bit srwd operates in conjunction with the write protect signal ( wp ). with a combination of bit srwd and signal wp (srwd = "1", wp = "l"), this ic goes in hardware protect st atus. in this case, the bits composed of the nonvolatile memory in the status regist er (srwd, bp1, bp0) go in read only, so that the wrsr in struction is not be performed. www.datasheet.co.kr datasheet pdf - http://www..net/
125c operation spi serial e 2 prom for automotive rev.1.0 _00 S-25A256B seiko instruments inc. 11 1. 2 bp1, bp0 (b3, b2) : block protect bit bp1 and bp0 are composed of the nonvolatile memory . the area size of software protect against write instruction is defined by them . rewriting these bits is possible by the wrsr instruction. to protect the memory area against the write instruction, set either or both of bit bp1 and bp0 to "1". rewriting bit bp1 and bp0 is possible unless they are in hardware protect mode. refer to " ? protect operation " for details of block protect. 1. 3 wel (b1) : write enable latch bit wel shows the status of internal write enable latch. bit wel is set by the wren instruction only. if bit wel is "1", this is the status t hat write enable latch is set. if bit wel is "0", write enable latch is in reset, so that this ic does not receive the write or wrsr instruct ion. bit wel is reset after these operations; ? the power supply voltage is dropping ? at power-on ? after performing wrdi ? after the completion of write oper ation by the wrsr instruction ? after the completion of write operation by the write instruction 1. 4 wip (b0) : write in progress bit wip is read only and shows whether the internal memory is in the write operation or not by the write or wrsr instruction. bit wip is "1" during the write operation but "0" dur ing any other status. figure 9 shows the usage example. 000 000 000 00 s r w d b p 1 b p 0 s r w d b p 1 b p 0 s r w d b t pr p 1 b p 0 wel, wip wel, wip wel, wip cs si so rdsr instruction rdsr inst ruction rdsr instruction rdsr rdsr rdsr 11 11 write or wrsr instruction d2 d1 d0 figure 9 usage example of wel, wip bits during write 2. write enable (wren) before writing data (write and wrsr), be sure to set bit wr ite enable latch (wel). this instruction is to set bit wel. its operation is below. after selecting this ic by the chip select ( cs ), input the instruction code from se rial data input (si). to set bit wel, set this ic in the non-select status by cs at the 8th clock of the serial clock (sck). to cancel the wren instruction, input the clock different from a s pecified value (n = 8 clock) while cs is in "l". www.datasheet.co.kr datasheet pdf - http://www..net/
125c operation spi serial e 2 prom for automotive S-25A256B rev.1.0 _00 seiko instruments inc. 12 so sck wp cs si instruction high-z 12345678 high / low figure 10 wren operation 3. write disable (wrdi) the wrdi instruction is one of ways to reset bit write enable latch (wel). after selecting th is ic by the chip select ( cs ), input the instruction code from serial data input (si). to reset bit wel, set this ic in the non-select status by cs at the 8th clock of the serial clock. to cancel the wrdi instruction, input the clock different from a s pecified value (n = 8 clock) while cs is in "l". bit wel is reset after the operations shown below. ? the power supply voltage is dropping ? at power-on ? after performing wrdi ? after the completion of write oper ation by the wrsr instruction ? after the completion of write operation by the write instruction so sck wp cs si instruction high-z 12345678 high / low figure 11 wrdi operation www.datasheet.co.kr datasheet pdf - http://www..net/
125c operation spi serial e 2 prom for automotive rev.1.0 _00 S-25A256B seiko instruments inc. 13 4. read the status register (rdsr) reading data in the status regi ster is possible by the rdsr instruction. during the write operation, it is possible to confirm the progress by checking bit wip. set the chip select ( cs ) "l" first. after that, input the instruction code fr om serial data input (si). the status of bit in the status register is output from serial data output (s o). sequential read is available fo r the status register. to stop the read cycle, set cs to "h". it is possible to read the status register always. the bits in it are valid and can be r ead by rdsr even in the write cycle. however, during the write cycle in progr ess, the nonvolatile bits srwd, bp1, bp0 are fixed in a certain value. these updated values of bit can be obtained by inputting another new rdsr instruction a fter the write cycle has completed. contrarily, two of read only bits wel and wip are being updated while the write cycle is in progress. so sck wp cs si instruction high-z 12345678 high / low 9 10111213141516 outputs data in the status register b7 b6 b5 b7b0b1b2b3b4 figure 12 rdsr operation 5. write in the status register (wrsr) the values of status register (srwd, bp1, bp0) can be rewritten by inputting t he wrsr instruction. but b6, b5, b4, b1, b0 of status register cannot be rewritten. b6 to 4 are always data "0" when reading t he status register. before inputting the wrsr instruction, set bit wel by the wren instruction. the operation of wrsr is shown below. set the chip select ( cs ) "l" first. after that, input the instruction c ode and data from serial data input (si). to start wrsr write (t pr ), set the chip select ( cs ) to "h" after inputting data or befor e inputting a rising of the next serial clock. it is possible to confirm the operat ion status by reading the value of bit wip during wrsr write. bit wip is "1" during write, "0" during any ot her status. bit wel is reset when write is completed. with the wrsr instruction, the val ues of bp1 and bp0; which determine the area size the users can handle as the read only memory; can be changed. besides bit srwd can be set or reset by the wrsr instruction depending on the status of write protect ( wp ). with a combination of bit srwd and write protect ( wp ), this ic can be set in hardware protect mode (hpm). in this case, the wrsr instruction is not be performed (refer to " ? protect operation "). bit srwd and bp1, bp0 keep the value which is the one prior to the wrsr instruction dur ing the wrsr instruction. the newly updated value is changed when the wrsr instruction has completed. to cancel the wrsr instruction, input the clock different from a s pecified value (n = 16 clock) while cs is in "l". www.datasheet.co.kr datasheet pdf - http://www..net/
125c operation spi serial e 2 prom for automotive S-25A256B rev.1.0 _00 seiko instruments inc. 14 so sck wp cs si instruction high-z 12345678 high / low 9 10111213141516 inputs data in the status register b7 b6 b5 b0b1b2b3b4 figure 13 wrsr operation 6. read memory data (read) the read operation is shown below. i nput the instruction code and the address from serial data input (si) after inputting "l" to the chip select ( cs ). the input address is loaded to the internal address counter, and data in the address is output from the serial data output (so). next, by inputting the serial clo ck (sck) keeping the chip select ( cs ) in "l", the address is automatically incremented so that data in the following address is sequentially output. the address counter rolls over to the first address by increment in the last address. to finish the read cycle, set cs to "h". it is possible to raise the chip select always during the cycle. during write, the read instruction code is not be accepted or operated. so sck wp cs si instruction high-z 12345678 high / low 91011 2122232425 16-bit address a15 a14 a13 a0a1a2a3 outputs the first byte d4d5d6d7 26 27 28 29 30 31 32 d0d1d2d3 d7 outputs the second remark the higher addresses a15 = don't care. figure 14 read operation www.datasheet.co.kr datasheet pdf - http://www..net/
125c operation spi serial e 2 prom for automotive rev.1.0 _00 S-25A256B seiko instruments inc. 15 7. write memory data (write) figure 15 shows the timing chart when inputting 1-byte data. input the instruction code, the address and data from serial data input (si) after inputting "l" to the chip select ( cs ). to start write (t pr ), set the chip select ( cs ) to "h" after inputting data or before inputting a rising of the next se rial clock. bit wip and wel are reset to "0" when write has completed. this ic can page write of 64 bytes. its function to transmit data is as same as byte write basically, but it operates page write by receiving sequential 8-bit write data as much data as page size has. input the inst ruction code, the address and data from serial data input (si) after inputting "l" in cs , as the write operation (page) shown in figure 16 . input the next data while keeping cs in "l". after that, repeat inpu tting data of 8-bit sequentially. at the end, by setting cs to "h", the write operation starts (t pr ). 6 of the lower bits in the address are automatically incremented ev ery time when receiving write data of 8-bit. thus, even if write data exceeds 64 bytes, t he higher bits in the address do not change. and 6 of lower bits in the address roll over so that write data which is previously input is overwritten. these are cases when the write instru ction is not acc epted or operated. ? bit wel is not set to "1" (not set to "1" beforehand immediately before the write instruction) ? during write operation ? the address to be written is in the protect area by bp1 and bp0 to cancel the write instructi on, input the clock different fr om a specified value (n = 24 + m 8 clock) while cs is in "l". so sck wp cs si instruction high-z 12345678 high / low 91011 2122232425 16-bit address a15 a14 a13 a0a1a2a3 data byte 1 d4d5d6d7 26 27 28 29 30 31 32 d0d1d2d3 remark the higher addresses a15 = don't care. figure 15 write operation (1 byte) www.datasheet.co.kr datasheet pdf - http://www..net/
125c operation spi serial e 2 prom for automotive S-25A256B rev.1.0 _00 seiko instruments inc. 16 so sck wp cs si instruction high-z 12345678 high / low 9 1011 22232425 16-bit address (n) a15 a14 a13 a0a1a2 data byte (n) data byte (n + x) d4d5d6d7 26 27 28 29 30 31 32 d0d1d2d3 d0d1d2d3 d4 remark the higher addresses a15 = don't care. figure 16 write operation (page) ? protect operation table 16 shows the block settings of write protect. table 17 shows the protect operation for this ic. as long as bit srwd, the status register write disable bit, in the status register is reset to "0" (it is in reset before t he shipment), the value o f status register can be changed. these are two statues when bit srwd is set to "1". ? write in the status register is possible; write protect ( wp ) is in "h". ? write in the status register is impossible; write protect ( wp ) is in "l". therefore the writ e protect area which is set by protect bit (bp1, bp0) in the status register cannot be changed. these operations are to set hardware protect (hpm). ? after setting bit srwd, set write protect ( wp ) to "l". ? set bit srwd completed setting write protect ( wp ) to "l". the timing during the cycle write to the status register is showed in " figure 6 valid timing in write protect " and " figure 7 invalid timing in write protect ". by inputting "h" to write protect ( wp ), hardware protect (hpm) is released. if the write protect ( wp ) is "h", hardware protect (hpm) does not function, software protect (spm) which is set by the protect bits in the status register (bp1, bp0) only works. www.datasheet.co.kr datasheet pdf - http://www..net/
125c operation spi serial e 2 prom for automotive rev.1.0 _00 S-25A256B seiko instruments inc. 17 table 16 block settings of write protect status register bp1 bp0 area of write protect addre ss of write protect block 0 0 0% none 0 1 25% 6000h to 7fffh 1 0 50% 4000h to 7fffh 1 1 100% 0000h to 7fffh table 17 protect operation mode wp pin bit srwd bit wel write protect block general block status register 1 x 0 write disable write disable write disable 1 x 1 write disable write enable write enable x 0 0 write disable write disable write disable software protect (spm) x 0 1 write disable write enable write enable 0 1 0 write disable write disable write disable hardware protect (hpm) 0 1 1 write disable write enable write disable remark x = don't care ? hold operation the hold operation is used to pause serial communications wit hout setting this ic in the non- select status. in the hold status, the serial data out put goes in "high-z", and both of t he serial data input and the serial clock go in "don't care". be sure to set the chip select ( cs ) to "l" to set this ic in the select status duri ng the hold status. generally, during the hold status, this ic hol ds the select status. but if setting this ic in the non-select status, the users can finish the operation even in progress. figure 17 shows the hold operation. these are two statuses when the serial clock (sck) is set to "l". ? if setting hold ( hold ) to "l", hold ( hold ) is switched at the same ti me the hold status starts. ? if setting hold ( hold ) to "h", hold ( hold ) is switched at the same time the hold status ends. these are two statuses when the serial clock (sck) is set to "h". ? if setting hold ( hold ) to "l", the hold status starts when the serial clock goes in "l" after hold ( hold ) is switched. ? if setting hold ( hold ) to "h", the hold status ends when the serial clock goes in "l" after hold ( hold ) is switched. sck hold hold status hold status figure 17 hold operation www.datasheet.co.kr datasheet pdf - http://www..net/
125c operation spi serial e 2 prom for automotive S-25A256B rev.1.0 _00 seiko instruments inc. 18 ? write protect function during the low power supply voltage this ic has a built-in detection circuit which operates with the low power supply voltage. this ic cancels the write operation (write, wrsr) when the power supply voltage drops and power-on, at the same time, goes in the write protect status (wrdi) automatically to reset bit wel. its detection and release voltages are 1.20 v typ. (refer to figure 18). to operate write, after the power suppl y voltage dropped once but rose to the volt age level which allows write again, be sure to set the write enable latch bit (w el) before operating write (write, wrsr). in the write operation, data in the address written during the low power supply voltage is not assured. cancel the write instruction set in write protect (wrdi) automatically release voltage ( +v det ) 1.20 v typ. detection voltage ( ?v det ) 1.20 v typ. power supply voltage figure 18 operation during the low power supply voltage ? input pin and output pin 1. connection of input pin all input pins in this ic have the cmos structure. do not set these pins in "high-z" during operation when you design. especially, set the cs input pin in the non-select status "h" during power-on/o ff and standby. the error write does not occur as long as the cs pin is in the non-sele ct status "h". set the cs pin to v cc via a resistor (the pull-up resistor of 10 k to 100 k ). if the cs pin and the sck pin change from "l" to "h" simultaneously, data may be input from the si pin. to prevent the error for sure, it is recommended to pull dow n the sck pin to gnd. in addition, it is recommended to pull up the si pin, the wp pin and the hold pin to v cc , or pull down these pins to gnd, respectively. connecting the wp pin and the hold pin to v cc directly is also possible when these pins are not in use. 2. equivalent circuit of input pin and output pin figure 19 and figure 20 show the equivalent circuits of input pins in this ic. a pull-up and pull-down elements are not included in each input pin, pay attention not to set it in t he floating state when you design. figure 21 shows the equivalent circuit of the output pin. this pin has the tri-st ate output of "h" / "l" / "high-z". 2. 1 input pin cs, sck figure 19 cs , sck pin www.datasheet.co.kr datasheet pdf - http://www..net/
125c operation spi serial e 2 prom for automotive rev.1.0 _00 S-25A256B seiko instruments inc. 19 si, wp, hold figure 20 si, wp , hold pin 2. 2 output pin so v cc figure 21 so pin ? precautions ? absolute maximum ratings: do not operate these ics in excess of the absolute maxi mum ratings (as listed on the data sheet). exceeding the supply voltage rating can cause latch-up. ? operations with moisture on this ic's pins may occu r malfunction by short-circuit between pins. especially, in occasions like picking this ic up from low temperature tank during the evaluation. be sure that not remain frost on this ic's pins to prevent malfunction by short-circuit. also attention should be paid in using on environm ent, which is easy to dew for the same reason. ? do not apply an electrostatic discharge to this ic that ex ceeds the performance ratings of the built-in electrostatic protection circuit. ? sii claims no responsibility for any and all disputes arising out of or in connection with any in fringement of the products including this ic upon patents owned by a third party. www.datasheet.co.kr datasheet pdf - http://www..net/

!"
#$% & $% %$ # % www.datasheet.co.kr datasheet pdf - http://www..net/

% # '$% '%%$% ($% $ $ %)*+ ,&$ $% !" -- " #$./"01#$2 * */ www.datasheet.co.kr datasheet pdf - http://www..net/

34 #5 $% (%$% ,) $% '($ '$ !" 6* 7-- *870" *6/* 96 9 9 www.datasheet.co.kr datasheet pdf - http://www..net/
www.sii-ic.com ? the information described herein is subject to change without notice. ? seiko instruments inc. is not responsible for any pr oblems caused by circuits or diagrams described herein whose related industrial properties, patents, or ot her rights belong to third parties. the application circuit examples explain typical applications of the products, and do not guarant ee the success of any specific mass-production design. ? when the products described herein are regulated produ cts subject to the wassenaar arrangement or other agreements, they may not be exported without authoriz ation from the appropriate governmental authority. ? use of the information described he rein for other purposes and/or repr oduction or copying without the express permission of seiko instrum ents inc. is strictly prohibited. ? the products described herein cannot be used as par t of any device or equipment affecting the human body, such as exercise equipment, medical equipment, security systems, gas equipment, or any apparatus installed in airplanes and other vehicles, without prior written permission of seiko instruments inc. ? although seiko instruments inc. exerts the greatest possible effort to ensure high quality and reliability, the failure or malfunction of semiconductor products may oc cur. the user of these products should therefore give thorough consideration to safety design, including redundancy, fire-prevention measures, and malfunction prevention, to prevent any accidents, fires, or community damage that may ensue. www.datasheet.co.kr datasheet pdf - http://www..net/

▲Up To Search▲

Price & Availability of S-25A256B

	To Download S-25A256B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .